The second report on “Machine Learning-Based Side Channel Analysis and Spy Hardware Recognition” by Assoc.Prof.Dr. Hoang Van Phuc, Institute of Integration, Military Technical Academy presented. The issue of information system security is becoming prominent, especially in the context of moving towards IoT-based smart cities. In recent times, there have been many studies reporting the possibility of using microchips and hardware tools to illegally collect information and attack information systems. Besides, integrated circuit (IC) fabrication technology has developed rapidly so that it can implement complex algorithms and intelligent processing techniques, but also lead to hardware security threats. at any step of the IC design and fabrication process. IoT systems in particular in the modern electronic system in general require hardware security with a focus on reliable cryptographic cores, device authentication solutions, prevention of chip (IC) tampering, detects spyware (Hardware Trojan) and trusted IoT device hardware (based on trusted processor). These topics have many new issues to solve such as implementation of physically ununlockable functions (PUF) for IoT device authentication, spyware detection, channel attack countermeasures side for the cryptographic core and hardware design for secure, reliable IoT nodes based on the RISC-V open source processor. Furthermore, the constant evolution of machine learning, especially deep learning, techniques that provide an effective approach to hardware security. Presentation of Assoc.Prof.Dr. Hoang Van Phuc also mentioned machine learning solutions in hardware security for secure IoT systems with a focus on machine learning-based side-channel analysis and spyware detection.
The third report mentions “Hardware architecture for Deep Spiking Neural Networks and some research results” by MSc. Nguyen Duy Anh presented. Recently, Deep Spiking Neural Network (DSNN) has emerged as a promising neuromorphic approach for various artificial intelligence applications, such as image classification, recognition. voice, robot control, etc on edge computing platforms. In this study, the team proposed a hardware-friendly training method for DSNN that allows the weights to be limited to a cubic format, thereby reducing memory space and power consumption. . Software simulations on MNIST and CIFAR10 datasets show that our training method can achieve accuracy of 97% for MNIST (3-layer fully connected network) and 89.71% for CIFAR10 (VGG16). ). To demonstrate the energy efficiency of the approach, we proposed a neural processing module for the trained DSNN implementation. When deployed as a fully connected 3-layer system, the system achieved an efficient power consumption of just 74nJ/image with a classification accuracy of 97% for the MNIST dataset. . We also considered a scalable design to support more complex network topologies as we integrated the neural processing module with an on-chip network with 3-way topology.
