In the context of rapidly advancing security technologies, encryption algorithms such as AES are regarded as highly secure, with virtually no theoretical vulnerabilities. However, real-world implementations in software and hardware reveal another risk, the leakage of information through side channels such as power consumption, execution time, or electromagnetic emissions. These seemingly harmless signals can be exploited to recover secret keys within a very short time, significantly compromising system security.
Studies have shown that with only around one hundred power-consumption traces and corresponding output data, an attacker can break AES on common microcontrollers within minutes, while traditional brute-force methods may take years. This highlights the urgent need to evaluate the security of hardware designs not only at the algorithmic level, but throughout the entire execution and operation process.
However, current hardware security testing workflows involve multiple complex and costly steps. Designers must complete the register-transfer-level (RTL) description, perform synthesis and simulation, then fabricate prototype chips using ASIC technology or program them onto FPGAs in order to collect real power traces before evaluating security. If a vulnerability is discovered after fabrication, the entire manufacturing process becomes wasteful in both time and cost, especially for applications requiring high security such as banking cards, electronic identity cards, or defense equipment.
To solve this problem, the Smart Integrated Systems Laboratory (SISLAB) at the Information Technology Institute, Vietnam National University, Hanoi, has proposed a completely new approach: evaluating hardware security based on estimated power-consumption traces right from the design phase, before fabrication. Instead of collecting real power data from physical chips, this method estimates and simulates power traces using design-level information, such as timing models, power networks, and parasitic parameters, to approximate the circuit’s energy consumption during operation. These traces are then analyzed using common side-channel attack techniques such as Correlation Power Analysis (CPA) or Differential Power Analysis (DPA) to detect potential information-leakage points.
Thanks to this approach, designers can identify security vulnerabilities early, pinpoint circuit blocks with high leakage risk, and apply countermeasures during the design stage, such as masking, load balancing, or operation-time randomization. Early detection and mitigation not only help ensure device security, but also significantly reduce costs, development time, and risks in mass production.
This invention on hardware-security evaluation based on estimated power-consumption traces is not only technically significant but also reflects an innovative mindset in microelectronics design. It marks an important step toward shifting security validation from post-silicon to pre-silicon stages, strengthening the ability to develop secure and reliable hardware products for critical applications in finance, identity management, and national security.
