{"id":11367,"date":"2022-11-30T12:42:41","date_gmt":"2022-11-30T05:42:41","guid":{"rendered":"https:\/\/iti.vnu.edu.vn\/daotao\/?post_type=chuong-trinh-dao-tao&#038;p=11367"},"modified":"2022-12-08T15:17:50","modified_gmt":"2022-12-08T08:17:50","slug":"thiet-ke-vi-mach-nang-cao","status":"publish","type":"chuong-trinh-dao-tao","link":"https:\/\/iti.vnu.edu.vn\/daotao\/chuong-trinh-dao-tao\/thiet-ke-vi-mach-nang-cao","title":{"rendered":"Thi\u1ebft k\u1ebf vi m\u1ea1ch n\u00e2ng cao"},"content":{"rendered":"\t<section class=\"section\" id=\"section_1549241632\">\n\t\t<div class=\"bg section-bg fill bg-fill  bg-loaded\" >\n\n\t\t\t\n\t\t\t\n\t\t\t\n\n\t\t<\/div>\n\n\t\t\n\n\t\t<div class=\"section-content relative\">\n\t\t\t\n<div class=\"row row-small\"  id=\"row-100057943\">\n\n\t<div id=\"col-1506238689\" class=\"col small-12 large-12\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n<h3>\u0110\u1ec0 C\u01af\u01a0NG KH\u00d3A H\u1eccC<\/h3>\n<h2 style=\"color: #ac050f;\"><strong>THI\u1ebeT K\u1ebe VI M\u1ea0CH N\u00c2NG CAO<\/strong><\/h2>\n<div class=\"is-divider divider \" style=\"max-width: 65px; background-color: #ac050f;\"><\/div>\n<p><strong style=\"color: #ac050f;\">1. T\u1ed5ng quan n\u1ed9i d\u1ee5ng: <\/strong>Ch\u01b0\u01a1ng tr\u00ecnh &#8220;thi\u1ebft k\u1ebf vi m\u1ea1ch n\u00e2ng cao&#8221; bao g\u1ed3m hai ph\u1ea7n ch\u00ednh:<\/p>\n<p>a) L\u00fd thuy\u1ebft thi\u1ebft k\u1ebf n\u00e2ng cao:- T\u00ecm hi\u1ec3u v\u1ec1 c\u1ea5u tr\u00fac vi x\u1eed l\u00fd RISC-V v\u00e0 HAPS<\/p>\n<ul>\n<li style=\"list-style-type: circle;\">H\u1ecdc v\u1ec1 c\u1ea5u tr\u00fac RISC-V<\/li>\n<li style=\"list-style-type: circle;\">Chuy\u00ean s\u00e2u v\u1ec1 s\u1eed d\u1ee5ng HAPS-80<\/li>\n<\/ul>\n<p>b) Th\u1ef1c h\u00e0nh thi\u1ebft k\u1ebf:- Th\u1ef1c nghi\u1ec7m c\u1ea5u tr\u00fac RISC-V tr\u00ean HAPS-80<\/p>\n<p><strong style=\"color: #ac050f;\">2. Th\u1eddi l\u01b0\u1ee3ng kh\u00f3a h\u1ecdc: <\/strong>40 ti\u1ebft.<\/p>\n<p><strong style=\"color: #ac050f;\">3. M\u1ee5c ti\u00eau kh\u00f3a h\u1ecdc: <\/strong><\/p>\n<p>&#8211; Ki\u1ebfn th\u1ee9c: N\u1eafm \u0111\u01b0\u1ee3c ki\u1ebfn th\u1ee9c n\u00e2ng cao v\u1ec1 thi\u1ebft k\u1ebf, ph\u00e1t tri\u1ec3n c\u00e1c thi\u1ebft b\u1ecb vi \u0111i\u1ec7n t\u1eed \u0111ang \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng ng\u00e0y nay- K\u1ef9 n\u0103ng: S\u1eed d\u1ee5ng th\u00e0nh th\u1ea1o c\u00f4ng c\u1ee5 kh\u1ea3 tr\u00ecnh ph\u1ea7n c\u1ee9ng HAPS-80- Th\u00e1i \u0111\u1ed9, chuy\u00ean c\u1ea7n: N\u00e2ng cao t\u00ednh t\u00edch c\u1ef1c trong h\u1ecdc v\u00e0 t\u1ef1 h\u1ecdc<\/p>\n<p><strong style=\"color: #ac050f;\">4. \u0110\u1ed1i t\u01b0\u1ee3ng tham gia kh\u00f3a h\u1ecdc: <\/strong> T\u1ed1t nghi\u1ec7p \u0111\u1ea1i h\u1ecdc (ho\u1eb7c sinh vi\u00ean n\u0103m cu\u1ed1i) c\u00e1c ng\u00e0nh \u0111i\u1ec7n, \u0111i\u1ec7n t\u1eed, k\u1ef9 thu\u1eadt m\u00e1y t\u00ednh, c\u00f4ng ngh\u1ec7 th\u00f4ng tin<\/p>\n<p><strong style=\"color: #ac050f;\">5. Y\u00eau c\u1ea7u ki\u1ebfn th\u1ee9c: <\/strong>Ng\u01b0\u1eddi h\u1ecdc c\u1ea7n c\u00f3 c\u00e1c ki\u1ebfn th\u1ee9c c\u01a1 b\u1ea3n v\u1ec1 \u0111i\u1ec7n t\u1eed s\u1ed1, ki\u1ebfn tr\u00fac m\u00e1y t\u00ednh, c\u1ea5u ki\u1ec7n \u0111i\u1ec7n t\u1eed, thi\u1ebft k\u1ebf l\u00f4-gic s\u1ed1, t\u01b0 duy l\u1eadp tr\u00ecnh<\/p>\n<p><strong style=\"color: #ac050f;\">6. K\u1ef9 n\u0103ng \u0111\u1ea1t \u0111\u01b0\u1ee3c sau kh\u00f3a h\u1ecdc: <\/strong><\/p>\n<p>&#8211; T\u01b0 duy thi\u1ebft k\u1ebf ki\u1ebfn tr\u00fac RISC-V- S\u1eed d\u1ee5ng th\u00e0nh th\u1ea1o c\u00e1c c\u00f4ng c\u1ee5 kh\u1ea3 tr\u00ecnh ph\u1ea7n c\u1ee9ng HAPS-80<\/p>\n\t\t<\/div>\n\t\t\t\t\n<style>\n#col-1506238689 > .col-inner {\n  padding: 0px 10px 0px 10px;\n}\n<\/style>\n\t<\/div>\n\n\t\n\n<style>\n#row-100057943 > .col > .col-inner {\n  background-color: rgb(255, 255, 255);\n}\n<\/style>\n<\/div>\n\t\t<\/div>\n\n\t\t\n<style>\n#section_1549241632 {\n  padding-top: 0px;\n  padding-bottom: 0px;\n}\n#section_1549241632 .ux-shape-divider--top svg {\n  height: 150px;\n  --divider-top-width: 100%;\n}\n#section_1549241632 .ux-shape-divider--bottom svg {\n  height: 150px;\n  --divider-width: 100%;\n}\n<\/style>\n\t<\/section>\n\t\n\t<section class=\"section\" id=\"section_394145369\">\n\t\t<div class=\"bg section-bg fill bg-fill  bg-loaded\" >\n\n\t\t\t\n\t\t\t\n\t\t\t\n\n\t\t<\/div>\n\n\t\t\n\n\t\t<div class=\"section-content relative\">\n\t\t\t\n<div class=\"row row-small\"  id=\"row-1607125984\">\n\n\t<div id=\"col-1748428538\" class=\"col small-12 large-12\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n\n<style>\n    table tr:nth-child(odd){background-color:#fbedec;}\n<\/style>\n<table>\n<caption style=\"text-align: left;\">\n<h2 style=\"color: #ac050f;\">CH\u01af\u01a0NG TR\u00ccNH KHUNG<\/h2>\n<\/caption>\n<tbody>\n<tr>\n<th style=\"width: 10%; text-align: center; ;\">STT<\/th>\n<th style=\"width: 25%; text-align: center; ;\">T\u00caN CHUY\u00caN \u0110\u1ec0<\/th>\n<th style=\"width: 50%; text-align: center; ;\">N\u1ed8I DUNG<\/th>\n<th style=\"width: 15%; text-align: center; ;\">S\u1ed0 TI\u1ebeT<\/th>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">1<\/td>\n<td>\n<p style=\"\">Unit 1: T\u1ed5ng quan v\u1ec1 h\u1ec7 th\u1ed1ng HAPS Prototype<\/p>\n<p style=\"\">Unit 2: T\u1ed5ng quan v\u1ec1 h\u1ec7 th\u1ed1ng ph\u1ea7n c\u1ee9ng HAPS<\/p>\n<\/td>\n<td style=\"vertical-align: top;\">\n<ul style=\"\">\n<li>Quy tr\u00ecnh thi\u1ebft k\u1ebf FPGA v\u00e0 ASIC; Chuy\u1ec3n thi\u1ebft k\u1ebf ASIC sang nguy\u00ean m\u1eabu tr\u00ean FPGA; C\u00e1c IPs ph\u1ed5 bi\u1ebfn trong thi\u1ebft k\u1ebf ASIC; C\u00e1c IPs ph\u1ed5 bi\u1ebfn trong thi\u1ebft k\u1ebf FPGA; Chuy\u1ec3n \u0111\u1ed5i c\u00e1c thi\u1ebft k\u1ebf c\u00f3 k\u1ef9 thu\u1eadt ch\u1eb7n clock; Kinh nghi\u1ec7m thi\u1ebft k\u1ebf v\u1edbi h\u1ec7 th\u1ed1ng HAPS<\/li>\n<li>S\u1ea3n ph\u1ea9m v\u00e0 gi\u1ea3i ph\u00e1p c\u00f4ng ngh\u1ec7 v\u1edbi HAPS; C\u00e1c h\u1ecd trong HAPS; HAPS-SX, HAPS-80, HAPS-70; S\u01a1 \u0111\u1ed3 thi\u1ebft k\u1ebf Clock; B\u1ed9 k\u1ebft n\u1ed1i HapsTrack 3 (HT3); Module \u0111i\u1ec1u khi\u1ec3n; UMRBus; C\u00e1c bo m\u1ea1ch m\u1edf r\u1ed9ng v\u00e0 d\u00e2y n\u1ed1i<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">2<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 3: Quy tr\u00ecnh thi\u1ebft k\u1ebf v\u1edbi Protocompiler<\/p>\n<p style=\"\">Unit 4: C\u01a1 s\u1edf chu\u1ea9n b\u1ecb cho thi\u1ebft k\u1ebf v\u00e0 h\u1ec7 th\u1ed1ng<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>T\u1ed5ng quan v\u1ec1 quy tr\u00ecnh thi\u1ebft k\u1ebf; Kh\u00e1i ni\u1ec7m v\u1ec1 c\u01a1 s\u1edf d\u1eef li\u1ec7u; Quy tr\u00ecnh ph\u00e2n t\u00e1ch thi\u1ebft k\u1ebf; Quy tr\u00ecnh t\u1ed5ng h\u1ee3p thi\u1ebft k\u1ebf; Giao di\u1ec7n \u0111\u1ed3 h\u1ecda ng\u01b0\u1eddi d\u00f9ng; Lab1: Ph\u00e2n t\u00e1ch thi\u1ebft k\u1ebf v\u00e0 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng v\u1edbi m\u1ed9t thi\u1ebft k\u1ebf \u0111\u01a1n gi\u1ea3n<\/li>\n<li>\u0110\u1eb7c t\u1ea3 c\u1ee7a h\u1ec7 th\u1ed1ng m\u1ee5c ti\u00eau (TTS: Target System Specification); Bi\u00ean d\u1ecbch thi\u1ebft k\u1ebf; C\u00e0i \u0111\u1eb7t Protocompiler; Ti\u1ec1n ph\u00e2n t\u00e1ch thi\u1ebft k\u1ebf; \u01af\u1edbc l\u01b0\u1ee3ng chi ph\u00ed kh\u00f4ng gian; \u01af\u1edbc l\u01b0\u1ee3ng chi ph\u00ed kh\u00f4ng gian th\u1ef1c thi; C\u00e1c r\u00e0ng bu\u1ed9c c\u1ee7a thi\u1ebft k\u1ebf; Lab2: T\u1ea1o ra TSS<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">3<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 5: C\u01a1 s\u1edf ph\u00e2n t\u00e1ch thi\u1ebft k\u1ebf<\/p>\n<p style=\"\">Unit 6: Ph\u00e2n t\u00e1ch h\u1ec7 th\u1ed1ng n\u00e2ng cao (t\u00f9y ch\u1ecdn)<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Kh\u00e1i ni\u1ec7m v\u1ec1 ph\u00e2n t\u00e1ch t\u1ef1 \u0111\u1ed9ng; C\u00e1c b\u01b0\u1edbc \u0111\u1ec3 ph\u00e2n t\u00e1ch; \u0110\u1ecbnh tuy\u1ebfn cho ph\u00e2n t\u00e1ch\/h\u1ec7 th\u1ed1ng; R\u00e0ng bu\u1ed9c cho ph\u00e2n t\u00e1ch (PCF: Partitioning constraint); C\u00e1c l\u1ec7nh d\u00f9ng cho PCF<\/li>\n<li>Gh\u00e9p k\u00eanh ph\u00e2n chia th\u1eddi gian (TDM: Time-Division Multiplexing); TDM tr\u00ean h\u1ec7 th\u1ed1ng HAPS-70\/HAPS-80; X\u1eed l\u00fd reset\/\u0111\u1ed3ng b\u1ed9; Ph\u01b0\u01a1ng ph\u00e1p ph\u00e2n t\u00e1ch; Chi\u1ebfn l\u01b0\u1ee3c ph\u00e2n t\u00e1ch; \u0110\u1ecbnh tuy\u1ebfn cho h\u1ec7 th\u1ed1ng; Lab3: Ph\u01b0\u01a1ng ph\u00e1p ph\u00e2n t\u00e1ch<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 7: T\u1ea1o h\u1ec7 th\u1ed1ng (t\u00f9y ch\u1ecdn)<\/p>\n<p style=\"\">Unit 8: C\u01a1 s\u1edf v\u1ec1 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Quy tr\u00ecnh \u0111\u1ec3 t\u1ea1o h\u1ec7 th\u1ed1ng; Ph\u00e2n b\u1ed1 th\u1eddi gian; C\u00e1c r\u00e0ng bu\u1ed9c c\u1ee7a TDM; Quy tr\u00ecnh m\u00f4 ph\u1ecfng sau ph\u00e2n t\u00e1ch<\/li>\n<li>C\u00e1c l\u1ec7nh \u0111\u1ec1 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng trong Protocompiler; Thi\u1ebft l\u1eadp m\u00f4i tr\u01b0\u1eddng; Quy tr\u00ecnh \u0111\u1ec3 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng; Ti\u1ec1n \u00e1nh x\u1ea1\/\u00e1nh x\u1ea1\/\u0110\u1eb7t v\u00e0 \u0111\u1ecbnh tuy\u1ebfn; C\u00e1c file ri\u00eang cho Protocompiler; Lab4: T\u1ed5ng h\u1ee3p \u0111\u1ed9c l\u1eadp cho FPGA<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">5<\/td>\n<td style=\"vertical-align: top; \">\n<p style=\"\">Unit 9: T\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng n\u00e2ng cao (t\u00f9y ch\u1ecdn)<\/p>\n<p style=\"\">Unit 10: C\u01a1 s\u1edf v\u1ec1 g\u1ee1 l\u1ed7i (debug)<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>K\u1ebft qu\u1ea3 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng; C\u00e1c t\u00f9y ch\u1ecdn \u0111\u1ec3 \u00e1nh x\u1ea1; K\u1ef9 thu\u1eadt \u0111\u01b0\u1eddng \u1ed1ng; K\u1ef9 thu\u1eadt \u0111\u1ec3 t\u1ed1i \u01b0u h\u00f3a th\u1eddi gian; Chuy\u1ec3n \u0111\u1ed5i clock<\/li>\n<li>Quy tr\u00ecnh \u0111\u1ec3 g\u1ee1 l\u1ed7i; Quy tr\u00ecnh tr\u00ean h\u1ec7 th\u1ed1ng FDGA \u0111\u01a1n; Quy tr\u00ecnh tr\u00ean h\u1ec7 th\u1ed1ng \u0111a FDGA; M\u00f4i tr\u01b0\u1eddng th\u1ef1c thi c\u1ee7a Confpro &amp; Protocompiler; C\u00e1c r\u00e0ng bu\u1ed9c thi\u1ebft k\u1ebf v\u1edbi thi\u1ebft b\u1ecb; C\u00e1c b\u01b0\u1edbc \u0111\u1ec3 g\u1ee1 l\u1ed7i<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">6<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 11: G\u1ee1 l\u1ed7i n\u00e2ng cao (t\u00f9y ch\u1ecdn)<\/p>\n<p style=\"\">Unit 12: Kh\u1edfi \u0111\u1ed9ng h\u1ec7 th\u1ed1ng<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>C\u00e1c thi\u1ebft b\u1ecb v\u00e0 g\u1ee1 l\u1ed7i n\u00e2ng cao; C\u00e1c k\u1ef9 thu\u1eadt k\u00edch ho\u1ea1t n\u00e2ng cao; G\u1ee1 l\u1ed7i v\u1edbi truy v\u1ea5n s\u00e2u; Lab5: G\u1ee1 l\u1ed7i n\u00e2ng cao v\u1edbi h\u1ec7 th\u1ed1ng \u0111a FPGA v\u00e0 quy tr\u00ecnh ph\u00e2n t\u00e1ch\/t\u1ed5ng h\u1ee3p<\/li>\n<li>Ch\u1ebf \u0111\u1ed9 kh\u1edfi \u0111\u1ed9ng c\u1ee7a bo m\u1ea1ch; Thi\u1ebft l\u1eadp Confpro; C\u00e1c b\u01b0\u1edbc ki\u1ec3m th\u1eed bo m\u1ea1ch; B\u00e0i t\u1eadp th\u1ef1c t\u1ebf; Ki\u1ec3m th\u1eed tr\u1ef1c ti\u1ebfp tr\u00ean m\u1ea1ch<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">7<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 13: T\u1ea1o nguy\u00ean m\u1eabu c\u1ee7a h\u1ec7 th\u1ed1ng RISC-V s\u1eed d\u1ee5ng HAPS (gi\u1edbi thi\u1ec7u)<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Gi\u1edbi thi\u1ec7u v\u1ec1 RISC-V; B\u1ed9 Kit ph\u00e1t tri\u1ec3n ph\u1ea7n m\u1ec1m; M\u00f4 ph\u1ecfng m\u1ee9c h\u00e0nh vi c\u1ee7a h\u1ec7 th\u1ed1ng; M\u00f4i tr\u01b0\u1eddng l\u00e0m vi\u1ec7c; Lab: M\u00f4 ph\u1ecfng m\u1ed9t h\u1ec7 th\u1ed1ng RISC-V<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">8<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 14: T\u1ea1o c\u00e1c IPs cho nguy\u00ean m\u1eabu<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>S\u1eed d\u1ee5ng c\u00e1c IP c\u1ee7a Xilinx Vivado: B\u1ed9 nh\u1edb kh\u1edfi t\u1ea1o b\u1ed9 nh\u1edb, MIG IPS; S\u1eed d\u1ee5ng c\u00e1c IP ri\u00eang c\u1ee7a Synopsys (y\u00eau c\u1ea7u license cho c\u00e1c IPs): Xactor, UMRBus; K\u1ebft n\u1ed1i c\u00e1c IP c\u1ee7a Xilinx, Synopsys; Lab: T\u1ea1p MIG IPs<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">9<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 15: M\u00f4 ph\u1ecfng h\u1ec7 th\u1ed1ng RISC-V<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>M\u00f4 ph\u1ecfng s\u1eed d\u1ee5ng VCS; M\u00f4 ph\u1ecfng c\u1ee7a h\u1ec7 th\u1ed1ng nguy\u00ean m\u1eabu v\u1edbi IP c\u1ee7a Xilinx v\u00e0 Synopsys; Lab: M\u00f4 ph\u1ecfng c\u1ee7a h\u1ec7 th\u1ed1ng RISC-V v\u1edbi c\u00e1c IPs kh\u00e1c nhau<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">10<\/td>\n<td style=\"vertical-align: top;\">\n<p style=\"\">Unit 16: Th\u1ef1c thi h\u1ec7 th\u1ed1ng RISC-V<\/p>\n<p style=\"\">Unit 17: Ki\u1ec3m th\u1eed v\u00e0 g\u00f5 l\u1ed7i<\/p>\n<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Chu\u1ea9n b\u1ecb m\u00f4i tr\u01b0\u1eddng th\u1ef1c thi; Ch\u1ea1y protocompier \u0111\u1ec3 t\u1ea1o ra bit stream; Lab: Th\u1ef1c thi h\u1ec7 th\u1ed1ng<\/li>\n<li>L\u1eadp tr\u00ecnh cho FPGA; s\u1eed d\u1ee5ng JTAG \u0111\u1ec3 l\u1eadp tr\u00ecnh ph\u1ea7n m\u1ec1m; Ki\u1ec3m th\u1eed l\u1ea7n cu\u1ed1i v\u00e0 g\u1ee1 l\u1ed7i; Ki\u1ec3m th\u1eed h\u1ec7 th\u1ed1ng v\u1edbi ph\u1ea7n c\u1ee9ng v\u00e0 ph\u1ea7n m\u1ec1m<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\t\t<\/div>\n\t\t\t\t\n<style>\n#col-1748428538 > .col-inner {\n  padding: 0px 10px 0px 10px;\n}\n<\/style>\n\t<\/div>\n\n\t\n<\/div>\n\t\t<\/div>\n\n\t\t\n<style>\n#section_394145369 {\n  padding-top: 30px;\n  padding-bottom: 30px;\n}\n#section_394145369 .ux-shape-divider--top svg {\n  height: 150px;\n  --divider-top-width: 100%;\n}\n#section_394145369 .ux-shape-divider--bottom svg {\n  height: 150px;\n  --divider-width: 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