{"id":11366,"date":"2022-11-30T12:39:28","date_gmt":"2022-11-30T05:39:28","guid":{"rendered":"https:\/\/iti.vnu.edu.vn\/daotao\/?post_type=chuong-trinh-dao-tao&#038;p=11366"},"modified":"2022-12-08T15:18:16","modified_gmt":"2022-12-08T08:18:16","slug":"thiet-ke-vi-mach-co-ban","status":"publish","type":"chuong-trinh-dao-tao","link":"https:\/\/iti.vnu.edu.vn\/daotao\/chuong-trinh-dao-tao\/thiet-ke-vi-mach-co-ban","title":{"rendered":"Thi\u1ebft k\u1ebf vi m\u1ea1ch c\u01a1 b\u1ea3n"},"content":{"rendered":"\t<section class=\"section\" id=\"section_1124936978\">\n\t\t<div class=\"bg section-bg fill bg-fill  bg-loaded\" >\n\n\t\t\t\n\t\t\t\n\t\t\t\n\n\t\t<\/div>\n\n\t\t\n\n\t\t<div class=\"section-content relative\">\n\t\t\t\n<div class=\"row row-small\"  id=\"row-1727248595\">\n\n\t<div id=\"col-940931621\" class=\"col small-12 large-12\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n<h3>\u0110\u1ec0 C\u01af\u01a0NG KH\u00d3A H\u1eccC<\/h3>\n<h2 style=\"color: #ac050f;\"><strong>THI\u1ebeT K\u1ebe VI M\u1ea0CH C\u01a0 B\u1ea2N<\/strong><\/h2>\n<div class=\"is-divider divider \" style=\"max-width: 65px; background-color: #ac050f;\"><\/div>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">1. T\u1ed5ng quan n\u1ed9i d\u1ee5ng: <\/strong><\/p>\n<p style=\"text-align: justify; \">Ch\u01b0\u01a1ng tr\u00ecnh &#8220;thi\u1ebft k\u1ebf vi m\u1ea1ch c\u01a1 b\u1ea3n&#8221; bao g\u1ed3m hai ph\u1ea7n ch\u00ednh:<\/p>\n<p>a) L\u00fd thuy\u1ebft thi\u1ebft k\u1ebf c\u01a1 b\u1ea3n:- Ki\u1ebfn th\u1ee9c v\u1ec1 thi\u1ebft k\u1ebf l\u00f5i IP (v\u00ed d\u1ee5, thi\u1ebft k\u1ebf IP \u0111i\u1ec1u khi\u1ec3n ng\u1eaft)- Quy tr\u00ecnh thi\u1ebft k\u1ebf l\u00f5i IP- Ki\u1ec3m th\u1eed ki\u1ebfn tr\u00fac \u0111\u01b0\u1eddng truy\u1ec1n d\u1eef li\u1ec7u AMBA tr\u00ean FPGA- Thi\u1ebft k\u1ebf vi x\u1eed l\u00ed m\u1ec1m Microblaze- X\u00e2y d\u1ef1ng firmware, thi\u1ebft k\u1ebf v\u00e0 ki\u1ec3m th\u1eed tr\u00ean h\u1ec7 th\u1ed1ng tr\u00ean chipb) Th\u1ef1c h\u00e0nh thi\u1ebft k\u1ebf:- Thi\u1ebft k\u1ebf IP c\u01a1 b\u1ea3n v\u00e0 ki\u1ec3m th\u1eed tr\u00ean FPGA (v\u00ed d\u1ee5 nh\u01b0 AES-128)<\/p>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">2. Th\u1eddi l\u01b0\u1ee3ng kh\u00f3a h\u1ecdc: <\/strong>40 ti\u1ebft.<\/p>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">3. M\u1ee5c ti\u00eau kh\u00f3a h\u1ecdc: <\/strong><\/p>\n<p>&#8211; Ki\u1ebfn th\u1ee9c: N\u1eafm \u0111\u01b0\u1ee3c ki\u1ebfn th\u1ee9c c\u01a1 b\u1ea3n v\u1ec1 thi\u1ebft k\u1ebf, ph\u00e1t tri\u1ec3n c\u00e1c thi\u1ebft b\u1ecb vi \u0111i\u1ec7n t\u1eed \u0111ang \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng ng\u00e0y nay- K\u1ef9 n\u0103ng: S\u1eed d\u1ee5ng th\u00e0nh th\u1ea1o ng\u00f4n ng\u1eef m\u00f4 t\u1ea3 ph\u1ea7n c\u1ee9ng, s\u1eed d\u1ee5ng th\u00e0nh th\u1ea1o c\u00e1c c\u00f4ng c\u1ee5, ph\u1ea7m m\u1ec1m thi\u1ebft k\u1ebf- Th\u00e1i \u0111\u1ed9, chuy\u00ean c\u1ea7n: N\u00e2ng cao t\u00ednh t\u00edch c\u1ef1c trong h\u1ecdc v\u00e0 t\u1ef1 h\u1ecdc<\/p>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">4. \u0110\u1ed1i t\u01b0\u1ee3ng tham gia kh\u00f3a h\u1ecdc: <\/strong> T\u1ed1t nghi\u1ec7p \u0111\u1ea1i h\u1ecdc (ho\u1eb7c \u0111ang h\u1ecdc n\u0103m 3, n\u0103m cu\u1ed1i) c\u00e1c ng\u00e0nh \u0111i\u1ec7n, \u0111i\u1ec7n t\u1eed, k\u1ef9 thu\u1eadt m\u00e1y t\u00ednh, c\u00f4ng ngh\u1ec7 th\u00f4ng tin<\/p>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">5. Y\u00eau c\u1ea7u ki\u1ebfn th\u1ee9c: <\/strong>Ng\u01b0\u1eddi h\u1ecdc c\u1ea7n c\u00f3 c\u00e1c ki\u1ebfn th\u1ee9c c\u01a1 b\u1ea3n v\u1ec1 \u0111i\u1ec7n t\u1eed s\u1ed1, ki\u1ebfn tr\u00fac m\u00e1y t\u00ednh, c\u1ea5u ki\u1ec7n \u0111i\u1ec7n t\u1eed, thi\u1ebft k\u1ebf l\u00f4-gic s\u1ed1, t\u01b0 duy l\u1eadp tr\u00ecnh<\/p>\n<p style=\"text-align: justify; \"><strong style=\"color: #ac050f;\">6. K\u1ef9 n\u0103ng \u0111\u1ea1t \u0111\u01b0\u1ee3c sau kh\u00f3a h\u1ecdc: <\/strong><\/p>\n<p>&#8211; T\u01b0 duy thi\u1ebft k\u1ebf ph\u1ea7n c\u1ee9ng- Quy tr\u00ecnh thi\u1ebft k\u1ebf v\u00e0 ki\u1ec3m th\u1eed vi m\u1ea1ch s\u1ed1- S\u1eed d\u1ee5ng th\u00e0nh th\u1ea1o c\u00e1c c\u00f4ng c\u1ee5 h\u1ed7 tr\u1ee3 thi\u1ebft k\u1ebf v\u00e0 ng\u00f4n ng\u1eef m\u00f4 t\u1ea3 ph\u1ea7n c\u1ee9ng- Th\u1ef1c thi \u0111\u01b0\u1ee3c d\u1ef1 \u00e1n \u0111\u01a1n gi\u1ea3n (mini-project) v\u1ec1 thi\u1ebft k\u1ebf m\u1ea1ch<\/p>\n\t\t<\/div>\n\t\t\t\t\n<style>\n#col-940931621 > .col-inner {\n  padding: 0px 10px 0px 10px;\n}\n<\/style>\n\t<\/div>\n\n\t\n\n<style>\n#row-1727248595 > .col > .col-inner {\n  background-color: rgb(255, 255, 255);\n}\n<\/style>\n<\/div>\n\t\t<\/div>\n\n\t\t\n<style>\n#section_1124936978 {\n  padding-top: 0px;\n  padding-bottom: 0px;\n}\n#section_1124936978 .ux-shape-divider--top svg {\n  height: 150px;\n  --divider-top-width: 100%;\n}\n#section_1124936978 .ux-shape-divider--bottom svg {\n  height: 150px;\n  --divider-width: 100%;\n}\n<\/style>\n\t<\/section>\n\t\n\t<section class=\"section\" id=\"section_762671847\">\n\t\t<div class=\"bg section-bg fill bg-fill  bg-loaded\" >\n\n\t\t\t\n\t\t\t\n\t\t\t\n\n\t\t<\/div>\n\n\t\t\n\n\t\t<div class=\"section-content relative\">\n\t\t\t\n<div class=\"row row-small\"  id=\"row-163337540\">\n\n\t<div id=\"col-1606739781\" class=\"col small-12 large-12\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n\n<style>\ntable tr:nth-child(odd){background-color:#fbedec;}<\/style>\n<table>\n<caption style=\"text-align: left;\">\n<h2 style=\" color: #ac050f ;\">CH\u01af\u01a0NG TR\u00ccNH KHUNG<\/h2>\n<\/caption>\n<tr>\n<th style=\"width: 10%; text-align: center; \">BU\u1ed4I<\/th>\n<th style=\"width: 75%; text-align: center; \">N\u1ed8I DUNG<\/th>\n<th style=\"width: 15%; text-align: center; \">S\u1ed0 TI\u1ebeT <\/th>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">1<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Gi\u1edbi thi\u1ec7u v\u1ec1 quy tr\u00ecnh thi\u1ebft k\u1ebf ph\u1ea7n c\u1ee9ng, c\u00e1c k\u1ef9 thu\u1eadt v\u00e0 c\u00e1c c\u00f4ng c\u1ee5.<\/li>\n<dd>&#8211; Ng\u00f4n ng\u1eef m\u00f4 t\u1ea3 ph\u1ea7n c\u1ee9ng: VHDL\/Verilog\/SystemVerilog<\/dd>\n<dd>&#8211; C\u00f4ng c\u1ee5 m\u00f4 ph\u1ecfng: VCS\/Modelsim\/Vivado<\/dd>\n<dd>&#8211; Quy tr\u00ecnh thi\u1ebft k\u1ebf vi m\u1ea1ch s\u1ed1<\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh (Lab): M\u00f4 ph\u1ecfng m\u1ed9t thi\u1ebft k\u1ebf d\u01a1n gi\u1ea3n<\/li>\n<\/ul>\n<td style=\"vertical-align: top;  text-align: center;  \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">2<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Ch\u1ee7 \u0111\u1ec1 n\u00e2ng cao v\u1ec1 ng\u00f4n ng\u1eef m\u00f4 t\u1ea3 ph\u1ea7n c\u1ee9ng v\u00e0 ch\u01b0\u01a1ng tr\u00ecnh m\u00f4 t\u1ea3<\/li>\n<dd>&#8211; Thi\u1ebft k\u1ebf m\u1ea1ch l\u00f4-gic t\u1ed5 h\u1ee3p<\/dd>\n<dd>&#8211; Thi\u1ebft k\u1ebf m\u1ea1ch l\u00f4-gic tu\u1ea7n t\u1ef1<\/dd>\n<dd>&#8211; Thi\u1ebft k\u1ebf m\u00e1y tr\u1ea1ng th\u00e1i h\u1eefu h\u1ea1n<\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh (Lab): Thi\u1ebft k\u1ebf m\u1ed9t m\u1ea1ch s\u1ed1 \u0111\u01a1n gi\u1ea3n v\u00e0 vi\u1ebft testbench t\u1ef1 \u0111\u1ed9ng \u0111\u1ec3 ki\u1ec3m th\u1eed<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top;  text-align: center;  \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">3&#038;4<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Quy tr\u00ecnh thi\u1ebft k\u1ebf IP<\/li>\n<dd>&#8211; Th\u00e0nh ph\u1ea7n c\u1ee7a m\u1ed9t IP v\u00e0 c\u00e1c giao di\u1ec7n k\u1ebft n\u1ed1i c\u1ee7a IP (interface)<\/dd>\n<dd>&#8211; Quy tr\u00ecnh thi\u1ebft k\u1ebf IP<\/dd>\n<dd>&#8211; X\u00e2y d\u1ef1ng testbench \u0111\u1ec3 ki\u1ec3m tra IP<\/dd>\n<dd>&#8211; X\u00e2y d\u1ef1ng c\u00e1c tr\u01b0\u1eddng h\u1ee3p ki\u1ec3m th\u1eed (testcase) \u0111\u1ec3 m\u00f4 ph\u1ecfng c\u00e1c t\u00ednh n\u0103ng c\u01a1 b\u1ea3n c\u1ee7a IP<\/dd>\n<dd>&#8211; X\u00e2y d\u1ef1ng m\u1ed9t tr\u01b0\u1eddng h\u1ee3p ki\u1ec3m th\u1eed c\u1ee7a IP<\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh 1: Thi\u1ebft k\u1ebf m\u1ed9t IP \u0111\u01a1n gi\u1ea3n (LED driver ho\u1eb7c m\u1ed9t core AES)<br \/>\n                    <br \/>\n                    B\u00e0i th\u1ef1c h\u00e0nh 2: Vi\u1ebft m\u1ed9t testbench<br \/>\n                    <br \/>\n                    B\u00e0i th\u1ef1c h\u00e0nh 3: Ki\u1ec3m th\u1eed thi\u1ebft k\u1ebf (v\u1edbi c\u00e1c quy tr\u00ecnh n\u00e2ng cao v\u00e0 t\u00f9y ch\u1ecdn)\n                <\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center;  \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">5<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Thi\u1ebft k\u1ebf h\u1ec7 th\u1ed1ng truy\u1ec1n th\u00f4ng tr\u00ean chip:<\/li>\n<dd>&#8211; Bus AMBA AXI\/AHB<\/dd>\n<dd>&#8211; AXI Slave; AXI Master<\/dd>\n<dd>&#8211; Truy c\u1eadp b\u1ed9 nh\u1edb tr\u1ef1c ti\u1ebfp (Direct Memory Access) <\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh thi\u1ebft k\u1ebf m\u1ed9t giao di\u1ec7n k\u1ebf n\u1ed1i bus \u0111\u01a1n gi\u1ea3n s\u1eed d\u1ee5ng Xilinx Vivado v\u00e0 vi\u1ebft testbench \u0111\u1ec3 ki\u1ec3m th\u1eed thi\u1ebft k\u1ebf<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top;  text-align: center;  \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">6<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>T\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng v\u00e0 th\u1ef1c thi tr\u00ean FPGA: <\/li>\n<dd>&#8211; Gi\u1edbi thi\u1ec7u v\u1ec1 ph\u1ea7n m\u1ec1m Vivado<\/dd>\n<dd>&#8211; Thi\u1ebft k\u1ebf \u0111\u1ec3 t\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng<\/dd>\n<dd>&#8211; T\u1ea1o c\u00e1c r\u00e0ng bu\u1ed9c cho thi\u1ebft k\u1ebf<\/dd>\n<dd>&#8211; T\u1ed5ng h\u1ee3p ph\u1ea7n c\u1ee9ng v\u1edbi Vivado<\/dd>\n<dd>&#8211; Th\u1ef1c thi ph\u1ea7n c\u1ee9ng v\u1edbi Vivado<\/dd>\n<dd>&#8211; Ki\u1ec3m tra thi\u1ebft k\u1ebf sau khi th\u1ef1c thi v\u1edbi Dev kit <\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh: T\u1ed5ng h\u1ee3p v\u00e0 th\u1ef1c thi m\u1ed9t thi\u1ebft k\u1ebf \u0111\u01a1n gi\u1ea3n v\u1edbi Vivado<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">7<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>Gi\u1edbi thi\u1ec7u Microblaze v\u00e0 IP integrator<\/li>\n<dd>&#8211; S\u1eed d\u1ee5ng Vivado \u0111\u1ec3 t\u1ea1o ra m\u1ed9t vi x\u1eed l\u00fd m\u1ec1m (soft processor)<\/dd>\n<dd>&#8211; S\u1eed d\u1ee5ng Vivado IP category \u0111\u1ec3 t\u1ea1o ra m\u1ed9t h\u1ec7 th\u1ed1ng tr\u00ean chip (SoC) \u0111\u01a1n gi\u1ea3n tr\u00ean FPGA<\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh: S\u1eed d\u1ee5ng Vivado \u0111\u1ec3 t\u1ea1o ra m\u1ed9t SoC ch\u1ea1y tr\u00ean FPGA<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top;text-align: center;  \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center;  \">8<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>M\u00f4i tr\u01b0\u1eddng ph\u00e1t tri\u1ec3n ph\u1ea7n m\u1ec1m: <\/li>\n<dd>&#8211; Gi\u1edbi thi\u1ec7u v\u1ec1 Microblaze SDK<\/dd>\n<dd>&#8211; T\u1ea1o g\u00f3i h\u1ed7 tr\u1ee3 bo m\u1ea1ch (board supported package &#8211; BSP)<\/dd>\n<dd>&#8211; Vi\u1ebft ch\u01b0\u01a1ng tr\u00ecnh \u0111\u01a1n gi\u1ea3n ch\u1ea1y tr\u00ean SoC v\u1eeba t\u1ea1o <\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh: Vi\u1ebft ch\u01b0\u01a1ng tr\u00ecnh HelloWorld<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center; \">4<\/td>\n<\/tr>\n<tr>\n<td style=\"vertical-align: top; text-align: center; \">9<\/td>\n<td style=\"vertical-align: top; \">\n<ul>\n<li>T\u1ea1o m\u1ed9t IP t\u00f9y bi\u1ebfn: <\/li>\n<dd>&#8211; S\u1eed d\u1ee5ng c\u00f4ng c\u1ee5 Manage IP c\u1ee7a Vivado \u0111\u1ec3 t\u1ea1o ra m\u1ed9t IP t\u00f9y bi\u1ebfn v\u00e0 m\u1edf r\u1ed9ng h\u1ec7 th\u1ed1ng v\u1edbi giao di\u1ec7n k\u1ebft n\u1ed1i t\u00f9y bi\u1ebfn<\/dd>\n<li>B\u00e0i th\u1ef1c h\u00e0nh: T\u1ea1o m\u1ed9t AES IP t\u00f9y bi\u1ebfn v\u1edbi giao di\u1ec7n k\u1ebft n\u1ed1i AXI Slave v\u00e0 vi\u1ebft ph\u1ea7n m\u1ec1m t\u01b0\u01a1ng t\u00e1c v\u1edbi IP<\/li>\n<\/ul>\n<\/td>\n<td style=\"vertical-align: top; text-align: center;  \">8<\/td>\n<\/tr>\n<\/table>\n\n\t\t<\/div>\n\t\t\t\t\n<style>\n#col-1606739781 > .col-inner {\n  padding: 0px 10px 0px 10px;\n}\n<\/style>\n\t<\/div>\n\n\t\n\n<style>\n#row-163337540 > .col > .col-inner {\n  background-color: rgb(255, 255, 255);\n}\n<\/style>\n<\/div>\n\t\t<\/div>\n\n\t\t\n<style>\n#section_762671847 {\n  padding-top: 0px;\n  padding-bottom: 0px;\n}\n#section_762671847 .ux-shape-divider--top svg {\n  height: 150px;\n  --divider-top-width: 100%;\n}\n#section_762671847 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